设计收敛

设计收敛英語:)是集成电路设计过程中,反复设计、调整设计细节,以使目标电路逐渐满足一系列设计约束的过程。集成电路设计的每个步骤(例如静态时序分析布局布线等)都是极其复杂的过程,并形成了若干专门的学科进行研究。

外部链接

    • Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field of electronic design automation. In particular, this article is derived (with permission) from the introduction of Chapter 10, Volume II, Design Closure by John Cohn.

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