M-sequence
M-sequence（、、最大長度序列）是在基本的通訊電路設計中，所經常被利用到的一個虛擬隨機數位訊號Pseudo Random Sequence，其主要的方式是利用第一位與其他位暫存器的輸出值做ex-or來設計其第一位暫存器的輸入值。
參考文獻
- Golomb, Solomon W.; Guang Gong. . Cambridge University Press. 2005 [2013-12-14]. ISBN 978-0-521-82104-9. （原始内容存档于2014-01-07）.
外部連結
- Bristow-Johnson, Robert. . [2013-12-14]. （原始内容存档于2020-09-29）.—Short on-line tutorial describing how MLS is used to obtain the impulse response of a linear time-invariant system. Also describes how nonlinearities in the system can show up as spurious spikes in the apparent impulse response.
- Hee, Jens. (PDF). [2013-12-14]. （原始内容存档 (PDF)于2019-08-19）. —Paper describing MLS generation. Contains C-code for MLS generation using up to 18-tap-LFSRs and matching Hadamard transform for impulse response extraction.
- Kerr, Wesley. . Geoffrey Aguirre Lab. University of Pennsylvania. [2013-12-14]. （原始内容存档于2020-05-09）. ]
- . New Wave Instruments. 2005 [2013-12-14]. （原始内容存档于2018-10-01）.—Properties of maximal length sequences, and comprehensive feedback tables for maximal lengths from 7 to 16,777,215 (3 to 24 stages), and partial tables for lengths up to 4,294,967,295 (25 to 32 stages).
- Schäfer, Magnus. . Institute of Communication Systems and Data Processing, RWTH Aachen University. October 2012 [2013-12-14]. V1.4. （原始内容存档于2015-09-24）. A（binaural）room impulse response database generated by means of maximum length sequences]
- (PDF). Xilinx. July 1996 [2013-12-14]. XAPP052 v1.1. （原始内容存档 (PDF)于2021-01-25）.—Implementing lfsr's in FPGAs includes listing of taps for 3 to 168 bits
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.